The integrated circuit industry has, since its inception, maintained a remarkable growth rate by driving increased device functionality at lower cost. Leading edge devices today provide the computing power of computers that used to occupy entire rooms at a mere fraction of the cost. Many of today's low cost consumer devices include functionality that only a few years ago was unavailable at any cost, such as video cell phones, ultra-portable media players, and wireless or ultra wideband Internet devices. One of the primary enabling factors of this growth has been the ability of optical lithography processes to steadily decrease the smallest feature size that can be patterned as part of the integrated circuit pattern. This steady decline in feature size and cost while at the same time printing more features per circuit is commonly referred to as “Moore's Law” or the lithography “roadmap.”
The lithography process involves creating a master image on a mask, or reticle, then replicating that pattern faithfully onto the device wafers. The more times a master pattern is successfully replicated within the design specifications, the lower the cost per finished device or “chip.” Until recently, the mask pattern has been an exact duplicate of the desired pattern at the wafer level, with the exception that the mask level pattern may be several times larger than the wafer level pattern. This scale factor is then corrected during wafer exposure by the reduction ratio of the exposure tool. The mask pattern is typically formed by depositing and patterning a light absorbing material on a quartz or other transmissive substrate. The mask is then placed in an exposure tool known as a “stepper” or “scanner” where light of a specific exposure wavelength is directed through the mask onto the device wafers. The light is transmitted through the clear areas of the mask and attenuated by a desired amount, typically between 90% and 100%, in the areas that are covered by the absorbing layer. The light that passes through some regions of the mask may also be phase shifted by a desired phase angle, typically an integer fraction of 180 degrees. After being collected by the exposure tool, the resulting aerial image pattern is then focused onto the device wafers. A light sensitive material deposited on the wafer surface interacts with the light to form the desired pattern on the wafer, and the pattern is then transferred into the underlying layers on the wafer to form functional electrical circuits according to well known processes.
In recent years, the feature sizes being patterned have become significantly smaller than the wavelength of light used to transfer the pattern. This trend towards “sub-wavelength lithography” has resulted in increasing difficulty in maintaining adequate process margins in the lithography process. The aerial images created by the mask and exposure tool lose sharpness as the ratio of feature size to wavelength decreases. This ratio is quantified by the k1 factor, defined as the numerical aperture of the exposure tool times the minimum feature size divided by the wavelength. The lack of sharpness or image blur can be quantified by the slope of the aerial image at the threshold for image formation in the resist, a metric known as “edge slope,” or “normalized image log slope,” often abbreviated as “NILS.” The smaller the NILS value, the more difficult it becomes to replicate the image faithfully onto a large number of device patterns with sufficient control to yield economically viable numbers of functional devices. The goal of successful “low k1 lithography” processes is to maintain the highest NILS possible despite the decreasing k1 value, thereby enabling the manufacturability of the resulting process.
New methods to increase the NILS in low k1 lithography have resulted in master patterns on the mask that are not exact copies of the final wafer level pattern. The mask pattern is often adjusted in terms of the size of the pattern as a function of pattern density or pitch. Other techniques involve the addition or subtraction of extra corners on the mask pattern (“serifs,” “hammerheads,” and other patterns), and even the addition of geometries that will not be replicated on the wafer. These non-printing “assist features” may include scattering bars, holes, rings, checkerboards, or “zebra stripes” to change the background light intensity (“gray scaling”), and other structures, which are well documented in the literature. All of these methods are often referred to collectively as “Optical Proximity Correction,” or “OPC.”
The mask may also be altered by the addition of phase shifting regions that may or may not be replicated on the wafer. A large variety of phase shifting techniques has been described at length in the literature including alternate aperture shifters, double expose masking processes, multiple phase transitions, and attenuating phase shifting masks. Masks formed by these methods are known as “Phase Shifting Masks,” or “PSMs”. All of these techniques to increase NILS at low k1, including OPC, PSM, and others, are referred to collectively as “Resolution Enhancement Technologies,” or “RETs.” The result of all of these RETs, which are often applied to the mask in various combinations, is that the final pattern formed at the wafer level is no longer a simple replicate of the mask level pattern. In fact, it is becoming impossible to look at the mask pattern and simply determine what the final wafer pattern is supposed to look like. This greatly increases the difficulty in verifying that the design data is correct before the mask is made and wafers exposed, as well as verifying that the RETs have been applied correctly and that the mask meets its target specifications.
Simulation based approaches have been developed to verify the correctness of the design and mask layout before the mask is fabricated. One such approach is described in U.S. Pat. No. 7,003,758, entitled “System and Method for Lithography Simulation,” the subject matter of which is hereby incorporated by reference in its entirety and is referred to herein as “the simulation system.” Even with the best possible RET implementation and verification, it is still not possible to optimize every feature of a design. Some structures will often not be properly corrected due to limitations of the technology, implementation errors, or conflicts with neighboring features. The simulation system can identify specific features of the design that will result in unacceptably small process windows or excessive critical dimension (CD) variation within the normally expected range of process conditions, such as focus and exposure variation. These defective regions must be corrected before the mask is made. However, even in the best designs, there will be structures or parts of structures that can not be optimally corrected. Although these weak areas can produce good chips, they may have marginally acceptable process windows and are likely to be the first locations within the device that will fail under varying process conditions, either due to variations of the wafer processing conditions, the mask processing conditions, or a combination of both. These weak areas are referred to herein as “hot spots.”
A critical consideration for these hot spots is that while the structures in question may have marginally acceptable process windows if the mask is produced exactly as expected based on the design data, the process window may become unacceptably small if any variations in the mask-making process alter the patterned structure at the mask level in such a way as to reduce the available process window at the wafer level. The impact of hot spots on wafer level patterning, electrical behavior, and yield is thus a convolution of both the mask and wafer processes. While either process can be monitored separately, there does not currently exist a method and system to monitor the combined effect of both mask and wafer patterning processes to determine whether there are regions of the design with unacceptably reduced process windows.
In the prior art, the mask and wafer processes are monitored independently. Some metrology data is collected during the mask-making process, either at test locations in the scribe-line or of representative structures in the device. Designer intent may be captured by measuring specific features in the device portion of the mask that are known to be critical to the electrical performance of the device. Given the limitations of the existing metrology tools, the number of points measured is limited to on the order of ten to a few hundred points, while the actual device contains hundreds of millions to billions of features. The full mask pattern can also be inspected for large defects, but is incapable of detecting critical dimension errors on the order of just a few nanometers unless the defects cover a large area. Specific features or parts of features that will result in unacceptable CD variation at the wafer level can not be detected by the current inspection tools.
Similarly, the wafer manufacturing process has previously been monitored for both CD variation and defects. A typical prior art monitoring system includes an image sensor unit having resolution-enhanced sensor elements and employs a method of aerial image acquisition. Such an image sensor unit and method of aerial image acquisition are described in U.S. Pat. No. 6,828,542, “System and Method for Lithography Process Monitoring and Control,” the subject matter of which is hereby incorporated by reference in its entirety. Such an image sensor unit can be loaded onto the wafer stage of a lithographic projection system in place of a regular production semiconductor wafer and be repeatedly exposed with the projected image from a mask in the same way as a production wafer.
With reference to FIG. 1, in one embodiment of the invention disclosed in the U.S. Pat. No. 6,828,542, aerial image sensing system 100 includes lithographic equipment 10 (for example, a stepper), an image sensor unit 102, and a processor/controller 104, for example, a computer and/or data or image processing unit. Lithographic equipment 10 may include a mirror 12, a light source 14 to generate light 16 at a certain exposure wavelength, illumination optics 18, projection optics 20, and a chuck 22. Chuck 22 secures image sensor unit 102 in a fixed location using, for example, electrostatic or vacuum forces.
The optics of lithographic equipment 10 (for example, light source 14, illumination optics 18, and projection optics 20) interacts with a mask 26 to project an aerial image onto image sensor unit 102. Mask 26, in one embodiment of the invention disclosed in the U.S. Pat. No. 6,828,542, may be a product-type mask; that is, a mask used to form circuits during integrated circuit fabrication. As such, mask 26 contains the pattern to be replicated or printed on a wafer that ultimately contains the circuit design (or a portion thereof) of the integrated circuit. In this embodiment, image sensor unit 102 may be employed to evaluate the interaction between mask 26 and lithographic equipment 10 (whether production or non-production equipment) as well as characterize the performance of lithographic equipment 10.
In another embodiment of the invention disclosed in the U.S. Pat. No. 6,828,542, mask 26 may be a test mask that is used to inspect, characterize and/or evaluate the optical characteristics or response of lithographic equipment 10. In this regard, mask 26 may include a fixed, predetermined and/or known pattern against which the aerial image collected, sensed, sampled, measured and/or detected by image sensor unit 102 will be evaluated, measured, and/or compared. In this way, any errors or discrepancies in the aerial images may be isolated or attributed to the optical system of lithographic equipment 10 and the performance of that system may be evaluated or characterized.
With continued reference to FIG. 1, image sensor unit 102 collects, measures, senses and/or detects the aerial image produced or generated by lithographic equipment 10 in conjunction with mask 26. Image sensor unit 102 provides image data, which is representative of the aerial image, to processor/controller 104. Processor/controller 104, in response, evaluates and/or analyzes that data to inspect, characterize and/or evaluate mask 26 and/or lithographic equipment 10 (or sub-systems thereof, for example, the optical sub-system). In this regard, processor/controller 104 implements data processing and analysis algorithms to process the data from image sensor unit 102 to reconstruct a full or partial aerial image, or to extract desired information directly without reconstructing a full or partial aerial image. Such image processing may involve deconvolution or other techniques familiar to those skilled in the art.
In addition, processor/controller 104 may use the data from image sensor unit 102 to perform and evaluate critical dimension measurements, and/or conduct defect inspection, for example, by comparing the measured aerial image to a pattern design database, or perform a die-to-die inspection if there are multiple dice on the same mask. Processor/controller 104 may also implement algorithms that conduct or perform resist modeling and/or integrated circuit yield analyses.
Processor/controller 104 may be employed as a control or operator console and data/image processing device. Processor/controller 104 may store algorithms and software that process the data representative of the aerial image (received from image sensor unit 102), extract information, manage data storage, and/or interface with users/operators. Processor/controller 104 may be located near or next to lithographic equipment 10 or in another locale, which is remote from lithographic equipment 10.
It should be noted that processor/controller 104 may be a stand-alone unit, as illustrated in FIG. 1, or partially or wholly integrated in lithographic equipment 10. In this regard, suitable circuitry in lithographic equipment 10 may perform, execute and/or accomplish the functions and/or operations of processor/controller 104 (for example, evaluation and/or analysis of the data representative of the aerial image collected, measured, sensed and/or detected at the wafer plane). Thus, in one embodiment, the inspection, characterization and/or evaluation circuitry/electronics may be partially or wholly integrated into lithographic equipment 10 and, as such, this “integrated system” may determine, assess, apply and/or implement appropriate corrective measures to enhance or improve its operation and thereby improve or enhance the quality, yield, and cost of integrated circuits manufactured therein.
It should be further noted that processor/controller 104 may also be partially or wholly integrated in, or on, image sensor unit 102. In this regard, some or all of the functions and operations to be performed by processor/controller 104 may be performed, executed and/or accomplished by suitable circuitry in, or on image sensor unit 102. As such, the collection and analysis of data representative of the aerial image may be less cumbersome in that a bus may be integrated and/or fabricated on or within image sensor unit 102 to facilitate communication of data and commands to/from the circuitry used to measure, detect and/or sense the aerial image and the circuitry used to evaluate and/or analyze the data representative of the aerial image.
With reference to FIG. 2, in one embodiment of the invention disclosed in the U.S. Pat. No. 6,828,542, an image sensor element array 106 of image sensor unit 102 is shown. Image sensor element array 106 includes a plurality of sensor elements 200, including 200ax to 200hx (x=1 to 8), that measure, sense, detect and/or collect incident energy or radiation.
In those instances where the dimensions of the active areas of sensor elements 200 are too large to provide a desired or required spatial resolution, it may be necessary to limit, restrict, and/or reduce these sensor cells' active areas that are exposed. Hence, image sensor element array 106 may include a patterned opaque film 204 that impedes, obstructs, absorbs, and/or blocks passage of photons or light of a given wavelength (that is, at the wavelength to be measured, sensed or detected by sensor elements 200). Opaque film 204 includes apertures 206, including 206ax to 206hx (x=1 to 8), so that active areas of sensor elements 200 are exposed only at apertures 206. As such, the spatial resolution of the energy measured by sensor elements 200 is enhanced or improved because the portion or area of each sensor element that is effectively exposed to and/or measures, senses, detects, and/or collects energy or radiation is limited or restricted.
Traditionally, the sampling plan and sensitivity in the prior art monitoring system for the wafer manufacturing process described above has not been informed by the known location of hot spots in the design or weak areas due to a combination of the design and the mask-making process. Wafer level metrology is limited to as few as 5 to 10 points within the field in a production process, or at most a few hundred points during initial mask qualification. Such limited samples are inadequate to fully sample the range of hot spots that might impact yield. Wafer inspection for pattern defects is even more limited than mask inspection due to the reduced signal to noise and image contrast of the resist patterns on the wafer as imaged by the wafer inspection tools. Some implementations have described a means of varying process conditions on the wafer to detect regions with locally limited process windows, but these methods are not informed by the map of expected hot spot locations, and are only sensitive to relatively large CD variations on the order of tens of nanometers. They are unable to discern CD variations on the order of 1 nm that may appear to be patterned correctly (no gross failure of the pattern) but will have a negative impact on device yield.
What is needed is a system to collect very high resolution metrology data (on the order of 1 nm sensitivity to CD variation) from a sample of thousands to millions of suspect hot spot locations across a range of process conditions and to ensure that this large number of locations is representative of all expected types of hot spots for the design and that they are distributed across the full spatial extent of the mask. Only by measuring the full effect of both mask-making variations and variation in the wafer imaging process can the full impact of the marginal design regions be accurately characterized and the process adjusted appropriately to optimize device performance and yield.